Method and resulting structure for manufacturing semiconductor substrates

ABSTRACT

A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate  210  and multiple semiconductor tiles  220  bonded to the surface of the metallic substrate  210.  The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Australian Provisional PatentApplication No. PS1122 filed Mar. 14, 2002, commonly assigned, andhereby incorporated by references for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT BACKGROUND OF THE INVENTION

The present invention relates generally to manufacturing substrates.More particularly, the invention provides a method and device forimproved semiconductor substrates to form advanced semiconductordevices. Merely by way of example, the invention has been applied to ametallic substrate that includes a plurality of panels and/or tiles,which are bonded on the substrate, for the manufacture of the advancedsemiconductor devices. But it would be recognized that the invention hasa much broader range of applicability.

As technology progresses, semiconductor manufacturers have continuallystrived to use ever larger wafers to obtain economies of scale, andconsequently lower the cost of individual semiconductor devices.Commonly, silicon crystal boules can be readily grown large enough toslice into 12 inch diameter wafers. The 12 inch wafers have beenproduced for single crystal silicon materials for a variety ofapplications. Although the single crystal silicon has many benefits,there are still numerous disadvantages.

Many conventional industries have been increasingly reliant on compoundsemiconductor devices fabricated from compound semiconductors such asgallium arsenide, indium phosphide, and gallium nitride. Unfortunately,integrated circuits made from these semiconducting compounds are stillrelatively expensive compared to circuits made from siliconsemiconductors. This cost difference is largely attributable to therespective material costs, and wafer processing costs. Other limitationsalso exist with compound semiconductor materials.

Compound semiconductor wafers are more prone to damage. For example,they are more brittle than conventional single crystal silicon wafers.Growing large crystal boules of compound semiconductor material isextremely difficult compared with growing large single crystal siliconboules. The maximum diameters for commercially-produced compoundsemiconductor wafers of gallium arsenide, indium phosphide and galliumnitride are respectively six inches, four inches and two inches inconventional commercial applications.

Larger compound semiconductor wafers would be desirable. Unfortunately,larger diameter wafers are difficult to make efficiently. Even if largerboules of compound semiconductor material could be produced, handlingthe resulting large-diameter compound semiconductor wafers wouldgenerally be problematic. Compound semiconductor wafers of the desiredthickness and diameter would be extremely fragile and prone to breakage.Here, the larger wafers would generally break due to the brittle natureof these semiconductor compounds. Accordingly, certain techniques havebeen proposed to manufacture larger compound semiconductor wafers usingan epitaxial grown layer.

As merely an example, a conventional process for fabricating compoundsemiconductor chips could be outlined in steps (i) to (vii) listedbelow.

-   -   (i) Grow epitaxial device layers on mono-crystalline substrate.    -   (ii) Pattern these epitaxial layers and other deposited        dielectric and metallic layers using photolithographic        techniques.    -   (iii) Bond wafers face-down to a temporary supporting substrate        after front-side process is complete.    -   (iv) Thin wafers by mechanical grinding or lapping back-side.    -   (v) Create “via holes” in the substrate, which provide a means        for connecting the back-side ground to appropriate front-side        ground connections.    -   (vi) Deposit a metal film on the wafer's back-side to provide a        ground plane, and coat the walls of the via holes, thereby        making contact with the front-side ground connections.    -   (vii) Dice wafer into individual chips.

In the above conventional process, wafers are typically 625 μm inthickness during steps (i), (ii) and (iii), and have sufficientmechanical strength to avoid breakage with careful handling. Wafers aretypically thinned to around 50 to 100 μm in thickness in step (iv).Thinning wafers has numerous advantages, which relate to:

-   -   (i) reducing the depth (and also the size) of via holes, as well        as parasitic inductance associated with the via holes;    -   (ii) conducting heat away from front-side devices towards the        back-side, which is normally attached to a heat sink; and    -   (iii) preventing electromagnetic resonance in the substrate at        high frequencies.

Handling thinned compound semiconductor wafers is often difficult, andcompound semiconductor wafers are commonly broken from step (iv)onwards. Breakage is costly, since most of the processing (steps (i) to(iii)) is already complete. The fragility of compound semiconductormaterials also causes breakages of resulting chip devices, and restrictsthe larger size of practical chip designs that use compoundsemiconductor materials. Here, larger sized compound semiconductormaterials are not practical to make efficiently.

In view of the above, a need exists for improved techniques forproducing and handling semiconductor wafers. In particular, a needexists for techniques suitable for assisting practical andcost-effective production of compound semiconductor devices.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, techniques for manufacturingsubstrates are provided. More particularly, the invention provides amethod and device for improved semiconductor substrates to form advancedsemiconductor devices. Merely by way of example, the invention has beenapplied to a metallic substrate that includes a plurality of panelsand/or tiles, which are bonded on the substrate, for the manufacture ofthe advanced semiconductor devices. But, it would be recognized that theinvention has a much broader range of applicability.

Described herein are techniques for producing a semiconductor wafercomposite from which semiconductor chips can be fabricated. Thesemiconductor wafer composite comprises a metallic substrate and one ormore semiconductor “tiles” bonded to the surface of the metallicsubstrate. These semiconductor tiles are formed by cutting asemiconductor wafer to a desired shape, as later described. Thedescribed techniques find particular application in fabricating compoundsemiconductor devices, but are also more broadly applicable to all typesof semiconductor wafers.

Multiple wafer tiles are advantageously bonded to the metallic substratebefore any front-side processing. The metallic substrate desirablyremains attached to the semiconductor material when the composite isdivided into individual chips. The semiconductor wafer composite iseffectively used as a single large semiconductor wafer, and can be usedto fabricate semiconductor devices in a similar manner. By way of themetal substrate, the composite is more durable and efficient.

The semiconductor tiles are advantageously square or rectangular, or oneor more other shapes able to be conveniently tessellated on the metallicsubstrate to efficiently cover the surface of the metallic substrate.These shapes are conventionally cut from the standard “clipped-circular”wafer shape.

In a specific embodiment, the invention provides a packaged compoundsemiconductor integrated circuit device. The packaged device includes acompound semiconductor substrate comprising a backside surface. Thedevice has a metal substrate bonded to the backside surface. The metalsubstrate provides mechanical support for the compound semiconductorsubstrate before being packaged. The metal support allows the compoundsemiconductor to be handled. The compound semiconductor has apredetermined size that is larger than a size that would be damaged ifit was free from the metal support according to preferred embodiments.Here, the large size would be too large for efficient handling withoutthe support structure. A support substrate is coupled to the metalsubstrate for packaging.

In a further alternative embodiment, the invention provides a bondedsemiconductor wafer composite for fabricating semiconductor devices. Thebonded semiconductor wafer has a metal support substrate. The metalsubstrate has a first diameter and an upper surface, which issubstantially planar. The metal support structure is characterized by afirst coefficient of thermal expansion parameter. The wafer also has aplurality of trapezoidal shaped tiles comprising a compoundsemiconductor material. The plurality of trapezoidal shaped tiles arebonded onto the upper surface of the metal support substrate. Each ofthe trapezoidal shaped tiles includes at least one edge, which isaligned with an edge of a different trapezoidal shaped tile. Each of theplurality of trapezoidal shaped tiles is characterized by a secondcoefficient of thermal expansion parameter. A eutectic bonding materialis coupled between each of the trapezoidal shaped tiles and a portion ofthe upper surface of the metal support substrate. The eutectic bondingmaterial provides a continuous mechanical and electrical contact betweenthe portion of the upper surface and the trapezoidal shaped tile. Thefirst coefficient of thermal expansion parameter is within apredetermined amount of the second coefficient of thermal expansionparameter. The predetermined amount is selected to reduce a possibilityof breakage of any portion of any trapezoidal shaped tile bonded to theportion of the upper surface of the metal substrate from a thermalinfluence, e.g., contraction, expansion. Each of the trapezoidal shapedtiles is derived from a compound semiconductor substrate of a seconddiameter, which is less than the first diameter associated with themetal substrate. Each of the trapezoidal shaped tiles comprises apredetermined thickness.

Various advantages can be achieved through use of a semiconductor tilebonded to a metallic substrate. The semiconductor wafer composite isless fragile than the semiconductor tile, and can thus be handled inlarger areas. As a result, cost savings can be achieved through largervolume fabrication.

In particular, compound semiconductor wafers that have been hithertoproduced from smaller diameter wafers can be processed in any effectivesize through the use of multiple semiconductor tiles. Consequently,existing fabrication equipment for treating 12 inch diameter siliconwafers can be used to fabricate compound semiconductor devices using thedescribed semiconductor wafer composite.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic representation of a view, from above,of a semiconductor wafer composite comprising a circular metallicsubstrate on which four square semiconductor tiles are bonded accordingto an embodiment of the present invention.

FIG. 2 is a simplified cross-sectional view corresponding with FIG. 1.

FIG. 3 is a simplified flowchart of a method involved in fabricatingsemiconductor chips from the semiconductor wafer composite of FIGS. 1and 2 according to an embodiment of the present invention

DETAILED DESCRIPTION OF THE INVENTION

According to the present invention, techniques for manufacturingsubstrates are provided. More particularly, the invention provides amethod and device for improved semiconductor substrates to form advancedsemiconductor devices. Merely by way of example, the invention has beenapplied to a metallic substrate that includes a plurality of panelsand/or tiles, which are bonded on the substrate, for the manufacture ofthe advanced semiconductor devices. But it would be recognized that theinvention has a much broader range of applicability.

A semiconductor wafer composite is described herein. The composite iswell suited to fabrication of compound semiconductor devices. Further,the composite has particular application in the context of large scaleproduction of such devices. The semiconductor wafer composite from whichthe individual semiconductor devices are fabricated is first described,followed by a procedure for high volume production of semiconductordevices using the described semiconductor wafer composite.

FIGS. 1 and 2 schematically represent a simplified semiconductor wafercomposite, using top and side views respectively according to anembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims herein. One ofordinary skill in the art would recognize many variations,modifications, and alternatives. The semiconductor wafer compositeeffectively replaces existing semiconductor wafers from whichsemiconductor chip devices are fabricated.

The described semiconductor wafer composite represented in FIGS. 1 and 2comprises a metallic substrate 210 upon which is bonded a number ofsemiconductor tiles 220.

FIG. 1 represents the metallic substrate 210 as circular in shape, andrepresents four abutting rectangular semiconductor tiles 220. The fourrectangular shapes shown in dotted outline represent further rectangularsemiconductor tiles 220 that may be bonded to the metallic substrate 210near the periphery of the metallic substrate 210, to more efficientlyuse the surface of the metallic substrate 210. The substrate ispreferably made from materials which have good electrical and thermalconductivity and whose coefficient of thermal expansion matches that ofthe semiconductor tiles. For example, CuMo, AlSi and Mo are suitablematerials. Preferably, the substrate is highly conductive withresistivity in the range 1 to 10 micro ohm centimeters (1-10×10⁻⁶ohm-cm) according to a specific embodiment. Alternatively, the materialcan be semiconductor according to other embodiments. The tiles 220 areclosely placed together, through perhaps not directly abutting. A slightspacing between wafer tiles 220 eases tile dimension accuracyrequirements and allows for slight thermal expansion gaps, if desirable.Indicative gap dimensions may be, for example, less than 5 μm.Preferably, each of the tiles should have a slight gap to separate themfrom each other to account for any differences in tolerances.Alternatively, the tiles are abutting each other to prevent or reduceimpurities (e.g., photoresist) from entering regions between the tilesaccording to other embodiments.

FIG. 2 is a side view that corresponds with FIG. 1. The peripheralsemiconductor tiles 220 depicted in dotted outline in FIG. 1 are notrepresented in FIG. 2. The metallic substrate 210 comprises a metallicbase layer 240, upon which is formed a metallic bonding layer 250. Themetallic base layer 240 may be formed of a suitable metal or alloys thatmatches the coefficient of thermal expansion (CTE) of the compoundsemiconductor material. For a gallium arsenide (GaAs) compoundsemiconductor tile 220, a suitable choice of metallic substrate 210 iscopper molybdenum (CuMo). The metallic bonding layer 250 is desirablyformed of tin (Sn) or indium (In) and gold (Au), or other suitablemetals having a relatively low melting point, and which form a eutecticalloy upon heating. In preferred embodiments, the eutectic alloy isprovided purely from compression and free from relative lateral movementbetween the tile and substrate.

The semiconductor tiles 220 comprise a working layer 260 of compoundsemiconductor material (such as gallium arsenide (GaAs)), and acomplementary bonding layer 270 preferably formed of a material thatassists the semiconductor tile 220 to adhere to the metallic substrate210. A suitable material is a combination of titanium (Ti) and gold(Au).

Surrounding the metallic base layer 240 and metallic bonding layer 250is a thin metallic coating layer 290, formed of a noble metal. Gold (Au)or platinum (Pt) is preferably used. The coating layer 290 seals themetallic substrate 210 from damage during subsequent fabrication ofsemiconductor devices from the semiconductor wafer composite. Thecoating layer 290 can be applied by evaporation/deposition techniques,or by electroplating, for example.

While components of the semiconductor wafer composite are describedabove with reference to FIGS. 1 and 2, various other associated featuresand advantages of the semiconductor wafer composite are described belowwith reference to a process for manufacturing the semiconductor wafercomposite. This manufacturing process is described herein with referenceto steps 310 to 330 of FIG. 3. Remaining steps 340 to 370 of FIG. 3describe subsequent steps in fabricating semiconductor devices from thesemiconductor wafer composite.

In a specific embodiment, each of the tiles has a specific size andshape. The metal substrate also has a desired shape and size. That is,the metal substrate has a diameter “dm”, which is chosen according tothe capabilities of the intended wafer processing equipment. Thisdimension is preferably selected from a set of industry diameters, e.g.,2 inch, 3 inch, 4 inch, 5 inch, 6 inch, 8 inch, 12 inch. The substrateis shaped to provide a “flat” on one part of the circumference that actsas an alignment reference, which is similar to conventional wafers.

Further, the substrate may be patterned to provide apertures which aidpackaging operations or which facilitate the coupling of signals offchip. For example, the apertures may be used to form slots which radiatehigh frequency signals off chip.

The tiles would be cut from circular compound semiconductor wafers ofradius “ds” where an integral number of wafer diameters “ds” equate tothe metal substrate diameter “dm” ie dm=n×ds where n is the smallestpossible integer. This relationship ensures the least number of tilesand minimum wastage of expensive compound semiconductor material incutting tiles to the appropriate shape. For example, four square tileswith 3 inch diagonal dimensions could be cut from 3 inch semiconductorwafers to cover a six inch metallic substrate in a 2×2 tile array. Ifonly 2 inch diameter semiconductor wafers were available, nine squaretiles with 2 inch diagonals could be prepared to cover a six inchsubstrate in a 3×3 array. Of course, there would be variousmodifications, alternatives, and variations.

Although the semiconductor wafer described above is illustrated using aspecific embodiment, there can be many variations, alternatives, andmodifications. For example, the metal substrate can be made of an alloyor other material, as well as other multilayered materials and the like,which have desirable electrical and thermal characteristics. The metalsubstrate can also be multi-layered, depending upon the application.Additionally, one or more of the tiles can be made of a differentmaterial on the substrate. These and other variations can be foundthroughout the present specification and more particularly below.

In a specific embodiment, a method for fabricating compoundsemiconductor devices involves, in overview, the steps listed below inTable 1. FIG. 3 flowcharts these steps, which are described in furtherdetail below. TABLE 1 Step 310 Multiple semiconductor wafers are thinned220. Step 320 The wafers 220 are cut to form semiconductor tiles. Step330 The semiconductor tiles 220 are bonded to the metallic substrate210. Step 340 Standard front-side processing techniques are used tofabricate devices. Step 350 Via holes are opened from the front-side tothe metallic substrate 210. Step 360 Via holes are metalized to makeground connections to the metallic substrate 210. Step 370 The metallicsubstrate 210 is cut to separate individual chips.

As shown above, the above steps are merely illustrative. Depending uponthe embodiment, certain steps can be further separated or even combinedwith other steps. Additional steps can be added depending upon theembodiment. Other steps can replace certain steps above. Accordingly,there can be many variations, modifications, and alternatives. Furtherdetails of each the steps can be found throughout the presentspecification and more particularly below.

Thinning Semiconductor Tiles—Step 310

Individual wafer tiles 220 are thinned according to existing processingtechniques. If the wafers break at this point, the associated cost isrelatively low since the front side of the semiconductor tile 220 hasnot been processed. According to a specific embodiment, tiles arethinned using a lapping/grinding and/or polishing operation. The tilescan be thinned to a thickness of about 50 to 100 microns according tocertain embodiments. According to a specific embodiment, tiles arethinned using a lapping /grinding and/or polishing operation.

Forming Semiconductor Tiles—Step 320

Semiconductor wafers are cut to form semiconductor tiles 220.Preferably, each of the tiles is provided using a scribing and breakingprocess. More preferably, scribing can be provided via a diamond stylus,laser cutting, or the like. These are preferably “standard” wafers thathave epitaxial layers grown on their front side and are ready for devicefabrication. The semiconductor tiles 220 are shaped such that thesesemiconductor tiles 220 can cover a planar surface with minimalintervening gaps. According to a specific embodiment, each of the tilesis formed along a crystalline plane, which provides an accurate shapeand form. Such accurate shape and form allows for alignment between eachof the tiles to reduce a possibility of gaps between each of the tiles.This also subsequently enables all tiles to be arranged on the metallicsubstrate with the same crystal orientation.

Bonding Tiles to Substrate—Step 330

A metallic substrate material is chosen to match the coefficient ofthermal expansion (CTE) of the chosen semiconductor over the requiredrange of processing temperatures. The substrate material is also chosenfor its strength, thermal and electrical conductivity and cost.Preferably, the substrate also has a high thermal conductivity to carryaway heat from an integrated device formed thereon. According to certainembodiments, the thermal conductivity of the metallic substrate can be165 Watts/m-Kelvin or greater.

For example, an alloy of approximately 80% molybdenum and 20% coppermatches the CTE of gallium arsenide and has suitable electrical andthermal conductivity. An advantage of using a metallic substrate 210 isthat the CTE can be adjusted by changing the composition of the metalalloy. No such adjustment is possible if a crystalline substrate such assilicon is used.

The metallic substrate 210 is polished on one face and its perimeter isshaped to suit large diameter wafer processing equipment. Preferably,polishing reduces a possibility of air gaps forming between the surfaceof the substrate and the tiles. The metallic substrate has a surfaceroughness no greater than a predetermined amount and a uniformity ofless than a certain amount across the substrate in certain embodimentsto facilitate the bonding process. According to certain embodiments, thesurface can also include a series of patterns and/or textures, whichprevent the formation of air bubbles, etc. and enhance the bondingprocess. This typically means the metallic substrate 210 is circular inshape (as represented in FIGS. 1 and 2). A minor flat on one side can beprovided, for compatibility with existing wafer processing equipment.

The metallic substrate 210 is preferably made as thin as possible so asnot to increase the weight or heat capacity of the composite structure.A typical thickness might be in the range 200 μm to 400 μm.

An inert coating layer 290 is then deposited on the metallic substrate210 if there is a risk that the substrate 210 might be effected bysubsequent semiconductor process chemistry. A thin layer (typically lessthan 1 μm in thickness) of a noble metal such as gold or platinum isgenerally suitable for this purpose. Preferably, the coating isnon-reactive with subsequent semiconductor processing steps. Othermaterials (such as silicon nitride) can also be used, provided suchmaterials have sufficient resistance to process chemistry andtemperatures used in the intended wafer processing steps.

The bonding layer 250 is deposited on the polished surface of themetallic substrate 210. This metallic bonding layer 250 is preferablymade from two or more metals that form a eutectic alloy on heating. Theoutermost layer is preferably a noble metal (such as gold) that preventsthe underlying layers from oxidising before and during bonding.Underlying layers may be formed of tin or indium. These metals arechosen such that the eutectic alloy forms at relatively low temperature(for example, 200 Degrees Celsius) and having formed, does not melt atthe elevated temperatures encountered during wafer processing. Thebonding layer may also serve as the inert coating layer for the metallicsubstrate.

A complementary bonding layer 270 is also deposited on the back-side ofeach thinned semiconductor wafer tile 220. This complementary bondinglayer 270 is also preferably metallic and its composition is chosen toprovide maximum adhesion to the semiconductor tile 220 over the range ofsubsequent processing temperatures. The preferred layer structures aretitanium/gold or titanium/platinum/gold, but many other combinations ofmetals are possible without departing from the scope and spirit of theinvention.

Numerous other bonding layer compositions are possible, and may bechosen to match particular processing requirements (such as maximumtemperature) of different semiconductor materials.

The use of metallic bonding layers offers the advantage of allowingbonding to occur at relatively low temperatures (for example, 200°).This ensures the epitaxial layer structure of the wafer tiles 220 is notdegraded. Non-metallic complementary bonding layers 290 such as silicon,polysilicon, silicon dioxide or silicon nitride may also be used.

Large gaps between semiconductor tiles 220 are desirably avoided as suchgaps may adversely affect the spin-deposition of photoresist. Thesemiconductor tiles 220 are preferably square or rectangular in shape.Such shapes allow arrays of rectangular chips to be efficientlycontained inside the semiconductor tiles 220, and also allowssemiconductor tiles 220 to be cut by scribing and breaking along crystalplanes, which are typically rectangular.

However, other tile shapes may also be used. Hexagonal tiles, forexample, may cover the surface of a circular substrate 210 moreefficiently than rectangular tiles. The preferred embodiment uses a setof non-uniform square or rectangular tiles as represented in FIG. 1. Theselected pattern semiconductor tiles 220 depends on the size of theavailable semiconductor wafers, and the size of the metallic substrate210.

The semiconductor tiles 220 are positioned on top of the polishedsurface of the metallic substrate 210, such that the semiconductor tiles220 preferably abut each other (or are closely spaced together) to forma substantially continuous semiconductor surface. Small gaps (forexample, of less than 5 μm) may be advantageous for the reasons notedabove. The semiconductor tiles 220 are arranged to ensure a commoncrystal axis orientation. The semiconductor tiles 220 and metallicsubstrate 210 are then subjected to a compressive force at elevatedtemperature, which causes a eutectic alloy to form and permanently bondthe semiconductor tiles 220 to the metallic substrate 210.

In a specific embodiment, bonding occurs by placing each of the tilesoverlying the metal substrate. A bonding layer such as those describedherein as well as others is also provided. Bonding occurs usingmechanical force between each of the tiles and the substrate to compressthe bonding layer. Heating is also provided. In a specific embodiment,heating and pressure (normal to the surface of the tiles and substrate)is applied, while maintaining each of the tiles free from lateralmovement with respect to the substrate to form, for example, a eutecticbonding layer between each of the tiles and the metal substrate. Ofcourse, there can be many variations, alternatives, and modifications.

Front-Side Processing of Composite—Step 340

The front-side of the composite wafer is now processed according tostandard semiconductor fabrication techniques. Fiducial alignment marksare provided on each tile 220, to allow for slight misalignments betweensemiconductor tiles 220. Individual chips are preferably arranged on thesemiconductor tiles 220, such that the chips are wholly contained withintiles 220 and do not span semiconductor tile boundaries.

Opening Via Holes—Step 350

Unlike existing semiconductor processes, which create via holes from theback-side of a wafer toward the front-side, via holes can be made fromthe front side toward the metallic substrate 210. The alignment of viaholes is thus simplified as this alignment is relative to other visiblefront-side features.

Metallizing Via Holes—Step 360

The presence of the metallic substrate 210 allows large areas of thesemiconductor tiles 220 to be removed in the via hole process withoutcompromising the structural strength of the composite wafer. This meansthat via hole “trenches” can be formed on the semiconductor tiles 220.These trenches are able to provide the following features:

-   -   (i) relatively low inductance ground connections compared to        ordinary round vias;    -   (ii) electromagnetic screening between adjacent circuits, which        is important as circuit densities increase;    -   (iii) chip separation outlines; and    -   (iv) contouring of the semiconductor wafer to achieve localized        heat spreading features.        Cutting into Individual Devices—Step 370

The individual chips are separated by cutting the metallic substrate 210either from the front-side or back-side depending on the capabilities ofthe process machinery.

Since each chip is supported by a portion of the metallic substrate 210,chip breakage is reduced during handling. Also, larger chips may befabricated. As a result, more functions/systems may be integrated on asingle chip. Such chips offer considerable cost savings by simplifyingengineering and production requirements.

The presence of the metallic substrate 210 on each chip also serves as aheat spreader, which is advantageous in high power applications.

Further Variations

One variation of the above-described fabrication procedure is to bondun-thinned wafer tiles 220 to the metallic substrate 210. Thesemiconductor tiles 220 may be subsequently thinned when bonded to themetallic substrate 210. This variation provides the advantages of“planarising” the semiconductor surface of the wafer composite duringthe thinning process. The epitaxial device layers are, as a consequence,grown on the wafer composite.

This revised procedure may provide economic benefits in certaincircumstances. Further, handling requirements of wafer tiles 220 beforebonding are relaxed as the semiconductor tiles 220 are of greaterthickness at this stage.

A metallic bonding layer 250 is described herein, though othertechniques may be used to affix the semiconductor tiles 220 to ametallic substrate 210. For example, adhesives adapted to thetemperature and chemical processing conditions involved in semiconductorfabrication may be used to adhere semiconductor tiles 220 to a metallicsubstrate 210.

The techniques described herein are suitable for manufacturingsemiconductor devices including those using composite semiconductorslarge-diameter composite metallic substrates. As well as other benefitsdescribed herein, the described techniques potentially offer improvedradio frequency performance, improved yield and lower costs througheconomies of scale.

Various alterations, modifications and substitutions can be made to thearrangements and techniques described herein, as would be apparent toone skilled in the relevant art in the light of this disclosure withoutdeparting form the scope and spirit of this invention.

1. A bonded semiconductor wafer composite for fabricating semiconductor devices, the bonded semiconductor wafer comprising: a metal support substrate having a first diameter, the metal support substrate including an upper surface, the upper surface being substantially planar, the metal support structure being characterized by a first coefficient of thermal expansion parameter; a plurality of trapezoidal shaped tiles comprising a compound semiconductor material, the plurality of trapezoidal shaped tiles being bonded onto the upper surface of the metal support substrate, each of the trapezoidal shaped tiles including at least one edge, the one edge being aligned with an edge of a different trapezoidal shaped tile, each of the plurality of trapezoidal shaped tiles being characterized by a second coefficient of thermal expansion parameter; a eutectic bonding material coupled between each of the trapezoidal shaped tiles and a portion of the upper surface of the metal support substrate, the eutectic bonding material providing a continuous mechanical and electrical contact between the portion of the upper surface and the trapezoidal shaped tile; wherein the first coefficient of thermal expansion parameter is within a predetermined amount of the second coefficient of thermal expansion parameter, the predetermined amount being selected to reduce a possibility of breakage of any portion of any trapezoidal shaped tile bonded to the portion of the upper surface of the metal substrate from a thermal influence; and wherein each of the trapezoidal shaped tiles being derived from a compound semiconductor substrate of a second diameter, the second diameter being less than the first diameter associated with the metal substrate; each of the trapezoidal shaped tiles comprising a predetermined thickness.
 2. A semiconductor wafer composite for fabricating a semiconductor device, the semiconductor wafer composite comprising: a metallic substrate; and at least one semiconductor tile bonded to the metallic substrate.
 3. The semiconductor wafer composite as claimed in claim 2, wherein the at least one semiconductor tile is sequentially (i) cut to a predetermined shape, (ii) thinned, and (iii) bonded to the metallic substrate.
 4. The semiconductor wafer composite as claimed in claim 2, wherein the at least one semiconductor tile is sequentially (i) thinned, (ii) cut to a predetermined shape, and (iii) bonded to the metallic substrate.
 5. The semiconductor wafer composite as claimed in claim 2, wherein the at least one semiconductor tile is sequentially (i) cut to a predetermined shape, (ii) bonded to the metallic substrate, and (iii) thinned.
 6. The semiconductor wafer composite as claimed in claim 2, wherein connections are formed between semiconductor devices on a front-side surface of the at least one semiconductor tile and the metallic substrate by etching apertures in semiconductor material from a front-side of the at least one semiconductor tile and patterning a metal layer across the resulting front-side surface and aperture walls.
 7. The semiconductor wafer composite as claimed in claim 6, wherein semiconductor material is removed from the at least one semiconductor tile to form elongated trenches arranged to form perimeters around portions of a surface of the at least one semiconductor tile.
 8. The semiconductor wafer composite as claimed in claim 2, wherein the semiconductor wafer composite is diced to form individual integrated circuits having metallic substrates.
 9. The semiconductor wafer composite as claimed in claim 2, wherein the metallic substrate comprises a metallic base layer, and a bonding layer to which the at least one semiconductor tile is bonded.
 10. The semiconductor wafer composite as claimed in claim 2, wherein the metallic substrate further comprises an inert coating layer that substantially covers at least part of the metallic base layer and/or the bonding layer.
 11. The semiconductor wafer composite as claimed in claim 2, wherein the at least one semiconductor tile comprises a compound semiconductor.
 12. The semiconductor wafer composite as claimed in claim 11, wherein the at least one semiconductor tile further comprises a complementary bonding layer suitable for adhering to the metallic substrate.
 13. The semiconductor wafer composite as claimed in claim 12, wherein the complementary bonding layer is predominantly formed of one or more metals, one of which is a noble metal.
 14. The semiconductor wafer composite as claimed in claim 9, wherein the bonding layer is predominantly formed of two or more metals that form a eutectic alloy when heated.
 15. The semiconductor wafer composite as claimed in claim 10, wherein the inert coating layer is predominantly formed of a noble metal.
 16. The semiconductor wafer composite as claimed in claim 2, wherein the metallic substrate and the at least one semiconductor tile have respective coefficients of thermal expansion that are substantially similar values.
 17. The semiconductor wafer composite as claimed in claim 2, wherein the at least one semiconductor tile has a substantially rectangular or square shape.
 18. A method of manufacturing a semiconductor wafer composite for fabricating a semiconductor device, the method comprising: providing a metallic substrate; and bonding at least one semiconductor tile to the metallic substrate.
 19. The method as claimed in claim 18, further comprising sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) thinning the at least one semiconductor tile, and (iii) bonding the at least one semiconductor tile to the metallic substrate.
 20. The method as claimed in claim 18, further comprising sequentially (i) thinning the at least one semiconductor tile, (ii) cutting the at least one semiconductor tile to a predetermined shape, and (iii) bonding the at least one semiconductor tile to the metallic substrate.
 21. The method as claimed in claim 18, further comprising sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) bonding the at least one semiconductor tile to the metallic substrate, and (iii) thinning the at least one semiconductor tile.
 22. The method as claimed in claim 18, further comprising the steps of: forming connections between semiconductor devices on a front-side surface of the at least one semiconductor tile and the metallic substrate by etching apertures in semiconductor material from a front-side of the at least one semiconductor tile; and patterning a metal layer across the resulting front-side surface and aperture walls.
 23. The method as claimed in claim 22, further comprising removing semiconductor material from the at least one semiconductor tile to form elongated trenches arranged to form perimeters around portions of the surface of the at least one semiconductor tile.
 24. The method as claimed in claim 18, further comprising dicing the semiconductor wafer composite to form individual integrated circuits having metallic substrates.
 25. The method as claimed in claim 18, further comprising forming the metallic substrate from a metallic base layer, and a bonding layer to which the at least one semiconductor tile is bonded.
 26. The method as claimed in claim 18, further comprising substantially covering at least part of the metallic base layer and/or the bonding layer with an inert coating layer.
 27. The method as claimed in claim 18, further comprising forming the at least one semiconductor tile with a working layer predominantly of a compound semiconductor.
 28. The method as claimed in claim 18, further comprising forming the at least one semiconductor tile with a complementary bonding layer suitable for adhering the at least one semiconductor tile to the metallic substrate.
 29. The method as claimed in claim 28, further comprising forming the complementary bonding layer predominantly of one or more metals, one of which is a noble metal.
 30. The method as claimed in claim 25, further comprising forming the bonding layer predominantly of two or more metals that form a eutectic alloy when heated.
 31. The method as claimed in claim 28, further comprising forming the inert coating layer predominantly of a noble metal.
 32. The method as claimed in claim 18, further comprising matching respective coefficients of thermal expansion of the at least one semiconductor tile and the metallic substrate to substantially similar values.
 33. The method as claimed in claim 18, further comprising of cutting a semiconductor wafer to a substantially rectangular or square shape to form the at least one semiconductor tile.
 34. A semiconductor wafer composite for fabricating a semiconductor device, the semiconductor wafer composite manufactured by a process comprising the steps of: providing a metallic substrate; and bonding at least one semiconductor tile to the metallic substrate.
 35. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) thinning the at least one semiconductor tile, and (iii) bonding the at least one semiconductor tile to the metallic substrate.
 36. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises sequentially (i) thinning the at least one semiconductor tile, (ii) cutting the at least one semiconductor tile to a predetermined shape, and (iii) bonding the at least one semiconductor tile to the metallic substrate.
 37. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) bonding the at least one semiconductor-tile to the metallic substrate, and (iii) thinning the at least one semiconductor tile.
 38. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises: forming connections between semiconductor devices on a front-side surface of the at least one semiconductor tile and the metallic substrate by etching apertures in semiconductor material from a front-side of the at least one semiconductor tile; and patterning a metal layer across the resulting front-side surface and aperture walls.
 39. The semiconductor wafer composite as claimed in claim 38, wherein the process further comprises removing semiconductor material from the at least one semiconductor tile to form elongated trenches arranged to form perimeters around portions of the surface of the at least one semiconductor tile.
 40. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises dicing the semiconductor wafer composite to form individual integrated circuits having metallic substrates.
 41. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises forming the metallic substrate from a metallic base layer, and a bonding layer to which the at least one semiconductor tile is bonded.
 42. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises substantially covering at least part of the metallic base layer and/or the bonding layer with an inert coating layer.
 43. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises forming the at least one semiconductor tile with a working layer predominantly of a compound semiconductor.
 44. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises forming the at least one semiconductor tile with a complementary bonding layer suitable for adhering the at least one semiconductor tile to the metallic substrate.
 45. The semiconductor wafer composite as claimed in claim 44, wherein the process further comprises forming the complementary bonding layer predominantly of one or more metals, one of which is a noble metal.
 46. The semiconductor wafer composite as claimed in claim 41, wherein the process further comprises forming the bonding layer predominantly of two or more metals that form a eutectic alloy when heated.
 47. The semiconductor wafer composite as claimed in claim 42, wherein the process further comprises forming the inert coating layer predominantly of a noble metal.
 48. The semiconductor wafer composite as claimed in claim 34, wherein the process further comprises matching respective coefficients of thermal expansion of the at least one semiconductor tile and the metallic substrate to substantially similar values.
 49. The method as claimed in claim 34, wherein the process further comprises cutting a semiconductor wafer to a substantially rectangular or square shape to form the at least one semiconductor tile.
 50. A semiconductor wafer composite suitable for fabricating a semiconductor device, the semiconductor wafer composite comprising: a metallic substrate comprising (i) a base metallic layer, (ii) a metallic bonding layer predominantly formed of two or metals that form a euctectic alloy when heated, and (iii) an inert coating layer predominantly formed of a noble metal; and multiple semiconductor tiles bonded to the metallic substrate by heating the semiconductor tiles and the metallic substrate when the semiconductor tiles and the metallic substrate are in physical contact, so that the semiconductor tiles bond to the metallic bonding layer via the inert coating layer.
 51. A packaged compound semiconductor integrated circuit device comprising: a compound semiconductor substrate comprising a backside surface; a metal substrate bonded to the backside surface, the metal substrate providing mechanical support for the compound semiconductor substrate before being packaged; and a support substrate coupled to the metal substrate for packaging. 